Smaller Faster Less power consumption Cheaper (if you fabricate millions) 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nmĦ MICROWIND FINFET Microwind’s FinFET implementation based on a selection of 10 scientific publications The FinFET is used starting 14-nm node Layout, size and performances inspired from “average” 14-nm FinFET Scaling to 10-nm & 7-nm nodes Application note in progress Standard cell level parasitics assessment in 20nm BPL and 14nm BFF P.
Schuddinck, IEDM 2012 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits Ajay N. Some basic cells are accessible within a clickģ0 COMPILE LOGIC GATES Nor2 2 fins And3 4 finsģ1 COMPILE COMPLEX GATES A|(B&C) : yes we can (but not always win…)ģ2 INTERCONNECTS Generate a full stack of metal layers with min width and min spacing (min pitch) Edit > Generate > Bus Select “all layers” Select length 1µm as many available data are given in af/µm, Ω/µm, aH/µmģ3 10NM INTERCONNECTS Air Metal 8 Metal 7 Metal 5,6 Metal 3,4 Metal 1,2ģ4 CAPACITANCE Capacitance with upper layer Coupling capacitanceģ5 Simple, Double, Quadruple (and so does the cost.) Bhoj, IEEE VLSI, Vol 21, N☁1, 2013ħ The FinFET device has a different layout style than the MOS deviceįROM MOSFET TO FINFET >= 20nm Convert into FinFET creates fins from N-diffusion Only works for vertical gates Generate fins according to fin pitch (r308)Ģ9 COMPILE LOGIC GATES The cell compiler enables direct logic gate compilation, including dummy gates, 2 or 4 fins.
0 kommentar(er)
